Communications System Engineer – Xilinx – San Jose, CA

Communications System Engineer – Xilinx – San Jose, CA

8 November, 2018


Desired: System DesignFPGAC/C++4G/LTEUnit TestingMATLABSignal ProcessingADAS


Xilinx develops highly flexible and adaptive processing platforms that enable rapid innovation across a variety of technologies – from the endpoint to the edge to the cloud. Xilinx is the inventor of the FPGA, hardware programmable SoCs and the ACAP (Adaptive Compute Acceleration Platform), designed to deliver the most dynamic processor technology in the industry and enable the adaptable, intelligent and connected world of the future in a multitude of markets including Data Center (Compute, Storage and Networking); Wireless/5G and Wired Communications; Automotive/ADAS; Emulation & Prototyping; Aerospace & Defense; Industrial Scientific & Medical, and others. Xilinx’s core strengths simultaneously address major industry trends including the explosion of data, heterogeneous computing after Moore’s Law, and the dawn of artificial intelligence (AI).

Our global team is growing and we are looking for bold, collaborative and creative people to help us lead the industry transformation to build an adaptable intelligent world. We believe that by embracing diverse ideas, striving for excellence in all that we do, and working together as a unified team, we can accomplish anything. Come do your best work and live your best life as part of the ONEXILINX team!

Job Description

Xilinx is looking for a talented individual to join the Communications Signal Processing (CSPG) team in the position of Communications System Engineer. This team develops high performance and low cost digital front end (DFE) Radio designs for 5G base stations and DOCSIS RemotePHY applications with Xilinx’s unique RFSoC and Versal products and influences future device architectures. As Communications System Engineer, you will have the opportunity to work on DFE solution architecting, developing and testing, with a strong focus on Digital Pre-distortion (DPD) critical to Xilinx’s growth in sub-6GHz and mmwave 5G and cable communications applications.

Job Responsibilities

  • Static and signal dynamics testing in RF laboratory with 3GPP standards compliance with DPD and state of the art power amplifiers
  • Co-architecting, designing and optimizing floating and fixed-precision implementation of DPD and its system test designs with MATLAB and embedded C/C++
  • Work closely with algorithm and design teams in US, Europe and India offices
  • Candidate will participate in different phases of a project, including architecture, system design, coding, unit testing, integration and maintenance and customer support
  • Create internal and external facing detailed documentation (micro-architecture design documents, test specifications, test reports, user guides, etc.)

Technical Skill Requirements

  • PhD or MSEE preferred
  • Experience creating internal and/or external facing detailed documentation (micro-architecture documents, test plans, data sheets, user guides, application notes, etc.)
  • 5+ years of hands on experience in validating wireless radio designs on hardware in the lab
  • 5+ years of experience working on digital radio solutions with FPGA, DSP processors and/or SIMD and VLIW processor architectures
  • 5+ years of experience designing digital communication algorithms and solution with a strong emphasis on digital front end Radio (DFE) for 4G/5G PHY including Digital Predistortion (DPD), Crest Factor Reduction (CFR), Passive Intermodulation Correction (PIMC)
  • Hands-on experience with amplifier tuning and/or RF board tuning is desired
  • Ability to translate a software model into a hardware implementation
  • Excellent written and verbal communication skills in English
  • Experience creating internal and/or external facing detailed documentation (micro-architecture documents, test plans, data sheets, user guides, application notes, etc.)


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